Selectable cycle timer with plural outputs of different time intervals and automaticreset



y 1968 G. w. ARKSEY 3,383,525

SELECTABLE CYCLE TIMER WITH PLURAL OUTPUTS OF DIFFERENT TIME INTERVALSAND AUTOMATIC RESET Filed Jan. 21, 1966 lb /4a ,II n /1 cmcx MV MV MV MV4 20 X f /0-/ /2/ our- 5 PUT CO/NC. GATE ourl I I I l l l PUT /2-3CO/NC. GATE ourl 1 I I E 1 PUT +25 I i 1 l i i I01 26 #28 RESETINVENTOR. @RAYQON WELLS ARKSE) 3,383,525 SELECTABLE CYCLE TIMER WITHPLURAL OUT- PUTS OF DIFFERENT TIME INTERVALS AND AIJTQMATIC RESETGraydon W. Arksey, Edmonton, Alberta, Canada, as-

signor to Chemcell Limited-Chemcell Limitee, a corporation of CanadaFiled Jan. 21, 1966, Ser. No. 522,131 15 Claims. (Cl. 307269) ABSTRACTOF THE DISCLOSURE In its various aspects, the present invention relatesto electronic gates and to electronic cycle timers.

A widely used form of timer uses a series of cams on a shaft to operatea number of switches at various times after the start of the cycle. Thecam shaft is operated by a small synchronous motor and a reduction geartrain. The total cycle duration is the time taken for a completerotation of the cam shaft, and this is usually established by choice ofan appropriate reduction gear train.

Cycle timers of this type have many disadvantages. Since the cams rotaterelatively slowly, each cam operates its switch gradually in at leastone direction to close or to open the contacts. This condition limitsthe life of the switches and leads to erratic switch operation. Theproblem is only partially met by resort to special snap-acting switches,or by using overly rugged contacts or by careful design of the controlcircuits to minimize contact erosion. O Secondly, the times of operationof the switches are determined only with limited repeatable accuracy.Particularly in the case of long cycle times and where the cycle callsfor certain switches to operate in close succession, the degree ofinaccuracy and inconsistency of conventional cam cycle timers is asource of trouble. Further, the on time of cam-operated switches can becontrolled only approximately, and this limitation becomes more seriousas the on time becomes short in relation to the total cycle time.Finally, the total cycle time is limited by 50 available gearing, sothat (for example) 3-minute timers and 4-minute timers may be made byassembling appropriate gears in the driving train, but the gear drive isnot flexible in the sense that the user may not be free to establish anintermediate cycle time that may be desired, such as a cycle timebetween 3 and 4 minutes. In any case, cycle timers that use cam contactsare subject to wear and all the other difliculties characteristic ofmechanical devices.

An object of the present invention resides in the pro- 60 vision of anelectronic analogue of such a cam cycle timer, for virtually eliminatingall the foregoing difliculties. More specifically, an object of thepresent invention resides in providing a novel cycle timer wherein thetotal time of the cycle can be determined with far greater flexibility,wherein switch action is sudden in both on and off operations, whereinthe on time of the sequence of switches can be accurately determined andmaintained consistently even where short on times and long total cycletimes are involved, and wherein mechanical wear and its consequences areavoided.

In achieving the foregoing objects, a novel cycle timer States Patent 0is provided in which a clock-pulse source supplies pulses to anelectronic pulse counter; a gate and set of selective switches connectedto the counter enable presetting a precise count of clock-pulseintervals at which a relay is to operate; a large number of such gatesand sets of selective switches enables a large number of times in thecycle when different relays are to operate; and one such gate and set ofswitches activates a reset circuit for the counter, to start a newcycle. A specific but important feature of such a cycle timer is theinclusion of a pair of gates and sets of count-presetting switches toturn on and then to turn off a relay and thereby to control the on timeof such a relay. This form of cycle timer characteristically producessudden operation of relay contacts, and the total cycle time that may beselected is limited only by the total capacity of the counter and theclockpulse interval selected. Operating points of all the relays areconsistently maintained and may be set at any time desired, limited onlyby the clock-pulse interval.

A further feature of this invention resides in the provision of a novelpreset counter circuit wherein any possible interaction between thecounter and the controlled circuit, particularly a large number ofcontrolled circuits, is reduced to a minimum.

A further object of the invention relates to novel gate circuits ofgeneral application wherein solid-state diodes or other one-wayconducting devices are used in such a manner that their leakage-currentcharacteristic is virtually or entirely eliminated as a concern. Inknown gates using many solid-state diodes, the combined leakage currentscan simulate the forward current to be expected in one diode, and inthis way leakage currents can simulate erroneously a failure ofagreement of the circuits compared by the gate.

In the illustrative embodiment of the invention detailed below, presetcounter circuits and the gates in these circuits are related in a novelmanner. The counter stages, as usual, include electronic devices whichoperate in either a high-conduction state or a block state. A gateconnected to many selected electronic devices of the counter maintainsan output device in one condition so long as any of the selectedelectronic devices is in its high-conduction state; and at this time oneor more of the diodes (or substitute devices) are in their conductingstate. When all the selected electronic devices of the counter change totheir blocked state, each gate releases the output device to operate asif it were actually separate from the counter stages. In one instance,the voltage on the gate is reduced and reversed so that a low value ofvoltage is applied to the diodes, and the circuit in other respects issuch as to make inconsequential the resulting combined leakage of thediodes in the gates. In another form, the voltage on the gate elementsis largely or entirely removed so that there can be no leakage currentand no leakage-current problems.

The nature of the invention in its various aspects, and further objects,novel features and advantages, will be more readily apparent from thefollowing detailed description of an illustrataive embodiment shown inthe accompanying drawing. In the drawing:

FIGURE 1 is a block diagram of a novel cycle timer illustrating certainfeatures of the present invention; and

FIGURE 2 is a diagram of portions of the cycle timer of FIG. 1 includingthe wiring diagrams of portions thereof, illustrating further featuresof the invention.

In FIG. 1, devices 19-1, 102, 10-3 are a series of units for operatingswitches in sequence at preset times. The three units 10 shown in thedrawing represent a much larger number of units normally included inpractical cycle timers of this form. Clock-pulse source 16 providesimpulses counted by stages '14.

Various values registered in the counter represent various elapsed timesfollowing the start of pulsecounting. Each gate 12 is adjustable torespond to a predetermined count. For this purpose each gate '12includes a series of semiconductor diodes 18 connected to a selected oneof two output points of a related counter stage 14 via two-positionswitch 20.

In the form of counter shown (and described in detail below) each stage14 includes two electronic devices, one of which is in a high-conductionstate while the companion device is blocked. When a particular device ofeach pair of devices in a counter stage is blocked, the stage is said torepresent 0. All the stages are reset to O at the start ofpulse-counting by means of gate 12' and reset pulse generator 10. Inresponse to successive pulses of a certain polarity input to eachcounter stage, its condition reverses repeatedly and represents 1 andthen 0, alternately. In response to each pulse, a previously blockeddevice forming part of the counter stage becomes highly conductive andthe companion device becomes blocked. In response to two input pulses,each stage delivers one triggering pulse to the next counter stage.

The count represented in the counter depends on the particularcombination of states or "1) of all the stages 14. By connecting diodes18 to the output points of the proper devices in stages 14, diodes 18 inany one gate 12 can provide an output signal only when the stages 14 arein a particular combination of "0 and 1 states. This represents apredetermined count. With each input pulse from clock-pulse source 16representing a discrete time interval, each gate 12 provides a signalcontrolling a respective output device at the end of a predeterminedtime interval following reset of all the counter stages to 0. Thepredetermined time intervals are selected by the adjustment of switches20.

The described apparatus represents a cycle timer that is the analogue.of mechanical cam-operated switches driven by a clock motor andreduction gearing. The novel cycle timer has many advantages. It isimmune to wear. The operation of each switch-operating unit 10 is suddenregardless of how slow may be the advance of the timer. (This will beappreciated by considering a practical embodiment, where each switchoperates abruptly despite an elapsed-time increment between clock pulsesof six seconds.) This feature gives the dual advantages of avoidinggradual or tease operation of the switches and of determining withprecisely repeating consistency the time of each switch operation. Incontrast, teaseoperation of cam switches is only partly avoided throughthe use of snap-acting switches; and operation of each cam switch at agiven time is limited as to repeatable accuracy to some substantialpercentage of the 360-degree cam rotation of the cams. Finally, theflexibility of cam timers driven by geared-down clock drive mechanismsis limited both as to accuracy of interval-selection and as to totalcycle time, the latter being limited to available gearing. In contrast,any desired accuracy of time-interval selection is readily achieved withthe foregoing cycle timer, using an appropriate clock-pulse interval andan appropriate number of stages 14; and the total cycle time is alsocapable of highly flexible selection merely by selective setting of theswitches in gate 12'.

FIG. 2 shows certain details of a practical embodiment of the invention,illustrating further novel features.

In FIG. 2, a conventional form of binary counter stage 14 isillustrated. This includes transistors 22 and 24, their respective loadresistors 26 and 28 providing output points A and B, and appropriatecross-coupled circuits between the collector of each transistor and thebase of the other. In counter stage 14, one transistor is blocked whilethe other is saturated. Input is supplied via coupling capacitor 30 to ajunction C of a pair of isolating diodes 32. Pulse output to the nextstage appears on line 33 connected to output point B. The cross-couplingcircuits mentioned above include biasing resistors 34, cross-couplingresistors 36 and capacitors 38.

In a well-known manner, successive input pulses of a given polarityreverse the states of the transistors 22 and 24 successively; and uponevery second reversal, a pulse of the given polarity appears on line 33for the next-following stage. As a term of reference, each transistorand its associated load, bias and coupling means is here called anelectronic device which is either blocked or in a highconduction state.The high-conduction state is the result of a clamping arrangement insome forms of known binary counter stages, but in the circuit shown thehigh-condom tion state is due to its operation at the saturation level.The load current of resistor 26 or 28 does not change due to other loadcurrents in lines 40 and 42 When the associated transistor is operatingin its high-conduction, saturated state. Typical circuit values with NPNtransistors 22 and 24 type TI 495 are: resistors 28 and 30, 10,000 ohms;resistors 34, 680,000 ohms; resistors 36, 150,000 ohms. The transistoremitters are connected to ground, at the junction of a collector supplyof plus 25 volts and a base bias supply of minus 25 volts.

Output points A and B of the counter stage 14 extend via lines 40 and 42to the selective terminals of switches 20, whose selector contact isconnected to a diode 18.

The common lead 46 of diodes 18 connected to switchoperating unit 10-1extends to a point D in a voltage divider. This consists of resistors48, and 52 connected between the collector supply and the bias supply oftransistor 54 whose emitter is grounded. Tap E of the voltage divider isconnected to the transistor base. Relay 56 with its contacts 56a is thecollector load. Diode 58 shunts relay 56 to accommodate the discharge ofits magnetic field when transistor 54 is switched from its on conditionto its blocked condition. In an example, resistor 48 is 150,000 ohms;resistor 50 is 150,000 ohms; resistor 52 is 470,000 ohms; the collectorand bias supplies are plus 25 volts and minus 25 volts, respectively,and transistor 54 is NPN type TI 495.

In operation, it may be assumed that transistor 22 is in itshigh-conduction state, bringing terminal A close to ground potential.The connected diode 18 is forwardconducting in this circuit condition,shifting point E below ground and driving transistor 54 to cut-oft. Inthis phase of operation, the small current in lead 46 is supplied bytransistor 22, but this presents no problem. Due to its saturatedoperating condition, transistor 22 can readily supply this current andlike currents in the leads 46 to additional output devices like 10-1.Moreover, some part of the current in lead 46 is derived from thetransistors of other counter stages that may happen to be in theirhigh.- conduction states. Output device 10-1 remains in its inactivestate, and accordingly relay 56 is deenergized, so long as any diode ofthe related gate 12 is connected to a high-conduction transistor in acounter stage 14.

It may now be assumed that the stage 14 in FIG. 2 has changed conditionand transistor 22 is blocked; and it may also be assumed that a likecondition prevails for every diode 18 in coincidence gate 12-1 connectedto line 46. Points A shift almost to the potential of the collectorsupply, here a positive potential, as determined by the voltage dividerconsisting of load resistor 26 and resistors 34 and 36 associated withtransistor 24. Points D also rise to a voltage level determined byvoltage divider 48, 50, 52. The voltage at point D is below that of thecounter-stage collector supply by an amount sufficient for diodes 18 tobe reverse-biased and thus blocked. Diodes 18 may carry some smallleakage current at this time; but any such current-even the combinedleakage currents of all the diodes of gate 12-can have only a minimaleflect on the voltage at point B that provides switching-on bias fortransistor 54. Furthermore, such diode leakage current and that of thediodes in all the other gates 12 have virtually no eifect on thecounterstage operation. A very stable condition exists when all diodes18 of a gate are blocked due to their connection to the collector of ablocked counter-stage transistor; for then device 10 1 is released foroperation under control of its own bias network.

Device 10-1 thus turns on in response to shift of all diodes 18 in therelated gate 12 into their blocked state. This condition provides a highdegree of mutual immunity between device 10-1 and the counter stages.

Device 10-1 remains on until the next clock pulse is registered in thecounter. Accordingly, contacts 56a of relay 56 remain in their operatedcondition for the duration of one clock pulse before returning to theirnormal condition.

Output device 10-1 is one of plural output devices of this type that maybe included in the complete apparatus. Output devices 10-2 and 10-3represent another form of gate-controlled switch-operating circuithaving operating characteristics in some respects similar to device 10-1and used in a practical embodiment with one or more devices 10- 1.

Output device 10-2 is connected by lead 62 to the common terminals ofthe several diodes 18 forming the gate 12-2 for device 10-2. As shown,the illustrated switch connected to the related diode 18 is set forcontrol by terminal B of the counter stage 14. Resistor 64 is interposedbetween the common gate lead 62 and the base of transistor 60. Base biasis supplied via resistor 66 which extends to the same voltage supplylevel as the collector supply in counter stage 14. In a practical eX-ample, transistor 60 is of the PNP type, with plus volts at the biassupply terminal and plus 12 volts for emitter reference potential. Thecollector load resistor 70 extends to minus 25 volts.

With these connections, so long as terminal B in the counter stage shown(or terminal B in any other counter stage connected to the gate 12 ofoutput device 10-2) is near ground potential due to the high-conductionstate of the related transistor 24, diode 18 is forward conducting, andthe base of transistor is biased .to turn this transistor on.

When the selected points A and B of all stages 14 connected by switches20 and diodes 18 to lead 62 shift close to the collector supplypotential (due .to blocking of transistor 22 or 24 selected by switches20) the base of transistor 60 shifts virtually to the same potential asthat of the collector supply in the counter stage. Transistor 60 is cut011.

There is then virtually no voltage difference across diodes 18 in gate12-2 of unit 10-2. Any sm-all voltage across the diode is in theback-biasing direction so there is little if any current fi-ow. Thisrepresents an enormous effective impedance in the gate circuit whendevice 10-2 is allowed to change its state as the result of coincidencein gate 12-2. A very high degree of isolation results between thecounter stages at one side of a particular gate 1.2 and the controlledoutput device 10-2 when the latter has been released by ,the gate and isturned oil by its own bias supply. In an example, resistor 64 is 1.0megohms and resistor 66 is 6.8 megohms.

Output device 10-2 and output device 10-3 are of identical form in thisillustrative apparatus. The switches 20 of gates 12-2 and 12-3 areadjusted so that a sequence of clock pulses drives the pulse-counter toreach coincidence in gate 12-2 first and later in gate 12-3. The out putof device 10-2 is coupled to one input point 72a of flip-flop 72 (abistable stage having two input points) and the output of device 10-3 iscoupled to input point 72b of flip-flop 72. A relay 74 having contacts74a is conneoted as a load operated by flip-flop 72. Relay 74 isdeenergized in the normal condition of the flip-flop, at the start of atiming cycle. When unit 10-2 responds to coincidence in gate 12-2,flip-flop 72 reverses and energizes relay 74. The on time for relay 74continues in effect after control potential at point 7 2a disappears anduntil coincidence in gate 12-3 causes device 10-3 to apply a reversingsignal to input lead 72b of flip-flop 72. Relay 74- is then deenergized.The on time of relay 74 can thus be determined precisely at a very shorttime interval, even at a one-clock-pulse period, despite a vastly largertotal time of the timing cycle.

The pair of output devices 10-2 and 10-3 and their gates 12-2 and 12-3shown, together with the related flipfiops 72 and relays 74 are only onepair among many. A practical form of this apparatus includes eighteenpairs of such units controlling the on times of eighteen relays.

Gate 12 in FIGS. 1 and 2 triggers a reset pulse genera-tor 10 for thecounter stages 14. This occurs at a time established by the setting ofthe switches 20 in gate 12'. Naturally this time is later than the timesettings of the other gates 12. The occurrence of coincidence in gate 12causes unit 10 to deliver a reset pulse to all the counter stages 14 viacommon lead 76 and an isolating diode 78 individual to each counterstage.

Reset pulse generator 10 is a monostable multivibrator, includingtransistors 80 and 82. Input to the base of transistor 80 is applied bygate 12' via lead 84 and coupling condenser 86. Resistor 88 extendsbetween lead 84 and the same positive voltage level as the collectorsupply of the counter stages. So long as any counter stage 14 has asaturated transistor connected via a diode 18 to lead 84, this leadremains at a level close to ground potential. Resistor 90 maintainscut-off bias on the base .of transistor 80. When coincidence develops ingate 12 due to all the connected counter output points shifting to theircollector-supply level, a positive-going pulse (in this example) iscoupled by coupling condenser 86. This pulse is provided by resistor 88,the only function of the gate being to release lead 84 from groundpotential. Leakage current in diodes 18 of gate 12 is o-f no concernhere since there is no voltage across the diodes when coincidence isreached. Isolation between the output device 10' and the counter stagesis complete during the time of coincidence in gate 12'.

In FIG. 2, lead 62 is one of many which are connected by diodes 18 andswitches 20 of other gates to the various output points A or B of theseveral counter stages in the whole apparatus more fully shown inFIG. 1. Likewise, leads 46 and 84 are connected by diodes 18 andswitches 20 to output points A and B of the counter stages. It may beassumed that many diodes 18 in corresponding gates 12 extend to anoutput point A or B of a counter stage that is at the voltage level ofthe collector supply in the counter, due to the blocked condition of therelated transistor in the counter; and at the same time, many otherdiodes of those gates extend to output points A and B of other counterstages that may be assumed to be in their high-conduction state and thusvery close to ground potential. At such a time the diode extending tothe output point A or B of a blocked counter-stage transistor is itselfblocked by virtue of its polarization. The common leads 46, 62, 84, etc.of the gates are all held near ground potential by the forwardconduction of those diodes extending to output points of other counterstages assumed now to be in their high-conduction condition. Theblocking action of those diodes 18 which extend to blocked transistors22, 24, etc. provides isolation between the blocked transistors of thecounter and those counter-stage transistors in their high-conductionstate.

When any of the gates 12-1, 12-2, 12, etc. is in the condition of havingall of its diodes 18 extending to blocked transistors in the counterstages, the lead 46, 62, 84, etc. of that gate is either at or at leastnear the +25- volt level of the output point A or B. Consequently,little or no reverse-current flow occurs in a gate in which none of thediodes is forward-conducting. Such limited-current condition has theimportant advantage of effectively imparting a high-impedancecharacteristic to each gate when none of the diodes thereof isforward-conducting. In turn, the input circuit of the output device canthen be made of large-valued resistors. This high-impedancecharacteristic makes practical the use of large numbers of gatesconnected in common to the counter-stage transistors. In a simulated camtimer, it is an advantage to be able to use many gates for operatinglarge numbers of switching devices 56, 74, etc. Certain switchingdevices 74 are operated once by gate 122 to close and later by anothergate 12-3 to open, thus requiring two gates per switching device. Asalready stated, the inclusion of many gates creates no special problemhere. Switching devices controlled by two gates acting successively arenot merely closed and then opened at accurate times in the total timingcycle, but they have accurately defined short or long on times,irrespective of how long may be the total time of the cycle timer.

The illustrative embodiment of the invention in its various aspects hasproved highly successful and is pr sently preferred, but nonetheless itis readily modified by those skilled in the art, as by omitting ormodifying some portions of the apparatus shown, and its various novelfeatures may be utilized in other applications. Consequently theinvention should be construed broadly in accordance with its full spiritand scope.

The embodiments of the invention in which an exclusive property orprivilege is claimed are defined as follows:

1. A gating network, including a plurality of electronic devices eachoperable in either a blocked state or a highconduction state, each saiddevice having a load providing an output point, an output device havingan input circuit providing a control point biased, in the absence ofinput current, to a level at least approaching that of the output pointof a blocked electronic device, and a gate comprising plural one-wayconductive solid-state devices connected in common to said control pointand severally connected to the output points of said electron c devicesfor providing current to said control point when the related electronicdevice is in its high-conduction state, said output device being in onestate in response to said bias level and being driven to a differentstate by input current to said control point from any of said one-Wayconductive solid-state devices in the forward conducting conditionthereof, each of said solid-state devices being polarized to beforward-conducting when its respective electronic device is in itshigh-conduction state, whereby said control point is released to assumeits bias level for causing response of the output device to the blockedstate of all of said electronic devices and the tendency of said one-wayconductive solid-state devices to contribute leakage current to saidcontrol point is minimal.

2. A gating network in accordance with claim 1, wherein each of saidelectronic devices is a transistor circuit in saturated condition when,in its high-conduction state.

3. A gating network in accordance with claim 1, wherein said inputcircuit of said output device includes series resistors forming avoltage divider providing a first tap constituting said control pointand providing a second top more remote from the level of the outputpoint of a said electronic device in its blocked state, said outputdevice including a transistor having a base connected to said secondtap, and said transistor having an emitter connected to a referencevoltage level approximated by the output point of the electronic devicein its high-conduction state.

4. A gating circuit in accordance with claim 1, wherein said electronicdevices have transistors of a first semiconductor type and said outputdevice has a transistor of a second semiconductor type opposite to saidfirst type, the emitter of said second-type transistor being connectedto a bias point between the levels of a said output point of a saidelectronic device when blocked and when in its high-conduction state,and the base of said second-type transistor having a bias resistorconnected to a voltage level that approximates that of said output pointin the blocked state of said electronic device.

5. A gating circuit in accordance with claim 1, wherein the inputcircuit of said output device includes a resistor and a capacitorconnected to form said control point, the resistor having anotherconnection to a voltage supply point approximating that of said outputpoint in the blocked state of said electronic device, and said capacitorhaving an opposite biasing connection, whereby the capacitor provides anoutput pulse as all of said electronic devices assume their blockedstate.

6. A gating network, including a plurality of pairs of electronicdevices each operable in either a blocked state or a highconductionstate, one such device of each pair being blocked while the companiondevice of that pair is in its high conduction state, an output devicehaving an input circuit providing a control point biased, in the absenceof input current, to a level at least approaching that of the outputpoint of a blocked electronic device, and a gate comprising pluralsolid-state diodes connected in common to said control point and saidgate including switching means for connecting each said diode to aselected electronic device of a respective one of said pairs forproviding current to said control Point when the electronic deviceconnected thereto by said switching means is in its high-conductionstate, said output device being in one state in response to said biaslevel and being driven to a different state by input current to saidcontrol point from any of said one way conductive solid-state devices inthe forward conducting condition thereof, each of said diodes beingpolarized to be forward-conducting when its respective electronic deviceis in its high-conduction state, whereby said control point is releasedto assume its bias level for causing respons of the output device to theblocked state of all the selected electronic devices and the tendency ofsaid oneway conductive solid-state devices to contribute leakage currentto said control point is minimal.

7. A gating network in accordance with claim 6 wherein plural gates andplural output devices as aforesaid are included, the output deviceshaving their control points connected to respective gates.

8. A gating network in accordance with claim 6 wherein plural gates andplural output devices as aforesaid are included, the output deviceshaving their control points connected to respective gates, and whereinsaid pairs of electronic devices are interconnected as a puls counter,further including clock pulse input means to the pulse counter wherebysaid output devices respond to the counter in timed succession asdetermined by the selective settings of the corresponding switchingmeans.

9. A gating network in accordance with claim 6 wherein said pairs ofelectronic devices are interconnected as a pulse counter, furtherincluding clock-pulse input means to the pulse counter whereby saidoutput device responds to the counter when a certain time is reached asdetermined by the selective setting of said switching means.

10. A gating network in accordance with claim 6 wherein a pair of gatesand a pair of output devices as aforesaid are included, said pair ofoutput devices having their control points connected, respectively, tothe common connections of said pair of gates, further including aswitching device and a bistable control device for said switchingdevice, said bistable device having respective reversing connections tosaid output devices for control thereby.

11. A gating network in accordance with claim 6 wherein said pairs ofelectronic devices are interconnected as a pulse counter, furtherincluding clock-pulse input means to the pulse counter, and whereinplural gates and plural output devices as aforesaid are included, theoutput devices having their control points connected to respectivegates, and wherein one of said output devices is a reset pulse generatorhaving reset connections to said pairs of electronic devices, wherebysaid output devices respond to the counter in timed succession asdetermined by the selective settings of the corresponding switchingmeans and said counter is automatically reset at timed intervals inconditions to start another timing cycle.

12. A gating network in accordance with claim 6 wherein said pairs ofelectronic devices are interconnected as a pulse counter, and whereinsaid output device includes a relay comprising contacts in a normalcondition in the normal state of the output device wherein all of saiddiodes are non-conducting, further including clock-pulse input means tothe pulse counter, whereby said relay contacts when operated in responseto the blocked state of all the selected electronic devices remains inits operated condition only during one clock-pulse period.

13. A simulated cam timer, including a pulse-counter comprising pluralinterconnected stages each including an electronic device thatalternately assumes a high-conduction state and a blocked state, saiddevice having an output point that assumes a first voltage level whensaid device is in its high-conduction state and a second voltage levelwhen said device is in said blocked state, a clock-pulse sourceconnected to an input point of said pulse-counter, a plurality of outputdevices each having an input biasing connection, and a plurality ofgates each connected between a respective one of said output devices andselected points of said pulse-counter for representing ditferent timeintervals, each of said gates including a plurality of one-wayconductive solid-state devices connected between said output point of arespective one of said electronic devices and the related input biasingvpoint and being polarized for forward conduction when its saidelectronic device is in its high-conduction state, said output devicebeing polarized to become operative when all of the one-way conductivedevices connected to the input biasing point thereof become blocked,

and reset coupling means connected between the pulsecounter and that oneof said output devices which represents the largest time intervals ofsaid gates for starting successive timing cycles.

14. A cycle timer, including a clock-pulse generator, an electroniccounter including interconnected counter units responsive to theclock-pulse generator, plural gating means each including switchesconnected to said counter units selectively for responding to differentpredetermined numbers of clock pulses registered in the counter, andplural output devices connected to said plural gating means,respectively, said output device which is connected to the gating meansset for the largest predetermined number being a reset pulse generatorand being connected to said counter unit for the start of a timingcycle, the others of said output devices having switching devicesoperated in succession at times predetermined by the settings of saidgating-means switches.

15. A cycle timer in accordance with claim 14, wherein at least certainof said switching devices are connected to respective pairs of saidpairs of output units for successive operation and return to normal soas to be in the operated condition during a precise preset timeinterval.

References Cited UNITED STATES PATENTS 2,519,184 8/1950 Grosdoff 328-483,129,339 4/1964 Fritzsche et al 30788.5 3,172,042 3/1965 Dawirs 328483,263,174 7/1966 Bjorkman et al 328--48 JOHN S. HEYMAN, PrimaryExaminer.

